1. Field of the Invention
The present invention relates generally to a digital computer or microcontroller memory system, and, more particularly, to a memory system which provides the simultaneous access to data by several data buses, and to a memory device which uses this system.
2. Description of the Prior Art
Simple processors are known that take the program code in bytes out of the memory synchronously with the executing program. The instruction, the instruction code which is one-byte-long, consumes one memory read cycle to take out the instruction code from the memory. The instruction, having two bytes long instruction code, consumes two memory read cycles to take the instruction code from the memory. Therefore, a longer instruction code consumes more processor time, regardless the function complexity thereof, due to which the available calculating performance is reduced.
Furthermore, there are powerful processors known as well which withdraw the program code out of the memory in advance and store it in the internal processor memory. In a suitable instance, the instruction code is taken out from the internal processor memory and used to perform the program. This enables to execute the program most swiftly and without processor time loss due to waiting for withdrawing the instruction code from the memory. However, such processors are more complicated and expensive.
Furthermore, the memory arrangement according to the U.S. Pat. No. 5,008,852 is known as well. To generate the signals addressing the memory locations in this solution, the address converting means are used. The address converting means convert the address which enters the memory to another address to address the memory locations. The address converting means comprise an adder circuit and a dividing circuit. There are some disadvantages of this solution because the address converting circuit is complicated and the address conversion lengthens out the memory access time.